1. Field of the Invention
The present invention relates to a phase control circuit and, more particularly, to a phase control circuit using an analog multiplier.
2. Description of Related Art
Analog multipliers are circuit blocks which output the product of two input signals. An analog multiplier which performs a multiplication of input signals including their polarities is called a "four-quadrant multiplier". Analog multipliers can be used not only for multiplication, but also for squaring, for division, and for producing square roots. Also, when an analog multiplier performs nonlinear multiplication, it functions as a balanced modulator. Since analog multipliers have a wide range of applications, many integrated circuits including analog amplifiers, such as high-frequency modulation/demodulation circuits, have been manufactured.
As an example of a major application of an analog multiplier, a phase control circuit will be described. A phase control circuit receives two input signals having a .pi./2 phase difference therebetween and a control signal to generate an output signal having a different phase which varies in accordance with the control signal. This type of phase control circuit is used in various circuits such as a circuit for processing a chrominance signal in a picture signal which is utilized in a color television.
A conventional phase control circuit utilizing an analog multiplier is shown in FIG. 1. The phase control circuit includes differential circuits 5 and 6 which are formed by pairs of transistors Q51 and Q52 and transistors Q61 and Q62, respectively. Each pair of transistors Q51 and Q52 and transistors Q61 and Q62 has emitter areas identical to each other. The emitters of transistors Q51 and Q52 are connected with each other and connected, through a terminal T4, to a constant current source C1 which supplies constant current I.sub.o, while the emitters of transistors Q61 and Q62 are connected with each other and connected, through a terminal T5, to a constant current source C2 which also supplies constant current I.sub.o. Signal sources S1 and S2 are connected to terminals T4 and T5 to supply the differential circuits 5 and 6 with input signals i(.phi..sub.o +.pi./2) and i(.phi..sub.o), which have a phase difference of .pi./2 therebetween. In this text and accompanying drawings, i(.phi..sub.o) and i(.phi..sub.o +.pi./2) are meant by current signals having a phase .phi..sub.o and .phi..sub.o +.pi./2, respectively.
The bases of transistors Q51 and Q62 are connected with each other and to a control terminal T1, while the bases of transistors Q52 and Q61 are connected with each other and to a control terminal T2. The collectors of transistors Q51 and Q61 are connected with each other and to an output terminal T3, while the collectors of transistors Q52 and Q62 are connected with each other and to a power supply line VCC.
In operation, a control voltage E is input between control terminals T1 and T2. In differential circuit 5, the base voltage of transistor Q51 with respect to the base voltage of transistor Q52 is equal to the control voltage E. In differential circuit 6, the base voltage of transistor Q61 with respect to the base voltage of transistor Q62 is equal to an inverted control voltage -E which is an inversion of the control voltage E. Assuming that base-to-emitter voltages of transistors Q51, Q52, Q61 and Q62 are V.sub.BE51, V.sub.BE52, V.sub.BE61 and V.sub.BE62, respectively, equations EQU E=V.sub.BE51 -V.sub.BE52, and -E=V.sub.BE61 -V.sub.BE62
hold, because the emitter voltages of transistors Q51 and Q52 of differential circuit 5 are equal to each other, and the emitter voltages of transistor Q61 and Q62 of differential circuit 6 are equal to each other.
Assuming that the emitter currents and saturation currents of the base-emitter junctions of transistors Q51, Q52, Q61 and Q62 are I.sub.E51, I.sub.E52, I.sub.E61 and I.sub.E62, and I.sub.S51, I.sub.S52, I.sub.S61 and I.sub.S62, respectively, the base-to-emitter voltages V.sub.BE51, V.sub.BE52, V.sub.BE61 and V.sub.BE62 are represented by the following equations: EQU V.sub.BE51 =(KT/q).multidot.ln(I.sub.E51 /I.sub.S51), EQU V.sub.BE52 =(KT/q).multidot.ln(I.sub.E52 /I.sub.S52), EQU V.sub.BE61 =(KT/q).multidot.ln(I.sub.E61 /I.sub.S61), EQU V.sub.BE62 =(KT/q).multidot.ln(I.sub.E62 /I.sub.S62),
wherein T is an absolute temperature, K is Boltzmann's constant, and q is electron charge.
By using these equations, equations for the control voltage E and for the inverted control voltage -E can be rewritten as follows: EQU E=(KT/q).multidot.ln(I.sub.E51 .multidot.I.sub.S52 /I.sub.E52 .multidot.I.sub.S51), (1) EQU -E=(KT/q).multidot.ln(I.sub.E61 .multidot.I.sub.S62 /I.sub.E62 .multidot.I.sub.S61). (2)
Since transistors Q51 and Q52 in the differential circuit 5, as well as transistors Q61 and Q62 in the differential circuit 6 have identical emitter areas to each other, and the saturation currents of the base-emitter junctions of these transistors are proportional to the emitter areas, I.sub.S51 is equal to I.sub.S52 while I.sub.S61 is equal to I.sub.S62. Substituting these relationships into equations (1) and (2), the following equations are obtained: EQU E=(KT/q).multidot.ln(I.sub.E51 /I.sub.E52), EQU -E=(KT/q).multidot.ln(I.sub.E61 /I.sub.E62).
By rearranging these equations, the following equations are obtained: EQU I.sub.E51 =(1/2){1+tanh (qE/2KT)}(I.sub.E51 +I.sub.E52), (3) EQU I.sub.E61 =(1/2){1-tanh (qE/2KT)}(I.sub.E61 +I.sub.E62). (4)
Assuming that common-base current amplification factors of transistors Q51 and Q61 are both .alpha., the collector currents of transistors Q51 and Q61 are represented by .alpha.I.sub.E51 and .alpha.I.sub.E61, respectively. Since the collectors of transistors Q51 and Q61 are both connected to output terminal T3, output current ip flowing through terminal T3 is the sum of the collector currents of transistors Q51 and Q61 and is represented by the following equation: EQU ip=(.alpha./2){1+tanh (qE/2KT)}(I.sub.E51 +I.sub.E52)+(.alpha./2){1-tanh (qE/2KT)}(I.sub.E61 +I.sub.E62). (5)
Input currents of the differential circuits 5 and 6, which are the sum of the emitter currents of transistors Q51 and Q52 (I.sub.E51 +I.sub.E52) and the sum of the emitter currents of transistors Q61 and Q62 (I.sub.E61 +I.sub.E62), respectively, are equal to the sum of currents output from signal source S1 and constant current source C1 and the sum of currents output from signal source S2 and constant current source C2, respectively.
Signal s1 (=i(.phi..sub.o +.pi./2)) and signal s2 (=i(.phi..sub.o)) output from signal source S1 and S2 are represented by the following equations: EQU s1=i(.phi..sub.o +.pi./2))=i.sub.o sin {.phi..sub.o +.pi./2)=i.sub.o cos .phi..sub.o, (6) EQU s2=i(.phi..sub.o)=i.sub.o sin .phi..sub.o. (7)
Using these equations (6) and (7) and the output current I.sub.o of the constant current sources C1 and C2, equation (5) can be rewritten to obtain the following equation: ##EQU1## Equation (8) is composed of a first term of i.sub.o and a second term of I.sub.o. The first term of i.sub.o represents the signal component sp of the output current ip, the signal component sp having a phase component sP and an amplitude component sA. When the first term is compared to signal s1 from signal source S1, the amplitude component sA of the output current ip is .alpha..multidot.(1/.sqroot.2).multidot..sqroot.1+tanh.sup.2 (qE/2KT) times as large as i.sub.o, and the phase component sP has a relative value of +tan.sup.-1 {tanh (qE/2KT)}+.pi./4. Accordingly, in the conventional phase control circuit, the amount of phase shift of the output current ip can be varied, together with variation of the amplitude, in accordance with the control voltage E. The second term (.alpha.I.sub.o) represents a DC component of the output current ip, which remains constant regardless of variation of the control voltage E.
Variations in the amplitude and the amount of phase shift of the signal component of output signal ip with respect to variation of the control voltage E will be described in more detail. To clarify the description, an assumption is made that the control voltage E varies in the range -.infin.&lt;E&lt;+.infin..
As is apparent from equation (8), the amplitude component sA (sA=(1/.sqroot.2).multidot..sqroot.1+tanh.sup.2 (qE/2KT)) and the phase component sP (sP=tan.sup.-1 {tanh (qE/2KT)}) of output signal ip include a common parameter X expressed by the following function: EQU X=tanh (qE/2KT) (9)
This is an odd function of E and a monotonously increasing function of E because of the relationship q/2KT&gt;0.
Moreover, since the value of tanh (qE/2KT) remains in the range of -1&lt;tanh (qE/2KT)&lt;1, control voltage E in the range of -.infin.&lt;E&lt;+.infin. has one-to-one correspondence to a bounded variation of parameter X in the range of -1&lt;X&lt;1. In other words, variations in the amplitude and the phase of the signal component of the output signal expressed in terms of parameter X which varies in the range of -1&lt;X&lt;1 equivalently represent actual variations of the amplitude and the phase when the control voltage E is varied in the range of -.infin.&lt;E&lt;+.infin.. Accordingly, for the purpose of simplicity, the amplitude and the phase of the signal component of the output signal will be shown as a function of parameter X represented by equation (9). Further, when necessary, E will be obtained through a reverse conversion of equation (9), i.e., by the following equation: EQU E=(2KT/q).multidot.tanh.sup.-1 X. (10)
Now, functions f.sub.1 (X), .phi..sub.1 (X) are defined as follows: ##EQU2##
By substituting equations (11) and (12) into equation (8), the following equation is obtained: EQU ip=.alpha.i.sub.o .multidot.f.sub.1 (X).multidot.sin {.phi..sub.o +.phi..sub.1 (X)}+.alpha.I.sub.o, (13)
wherein f.sub.1 (X), .phi..sub.1 (X) respectively correspond to the amplitude component sA and the phase component sP of signal component.
FIG. 2 is a graph showing functions of f.sub.1 (X) and .phi..sub.1 (X) defined above. As apparent from FIG. 2, .phi..sub.1 (X)=0 when parameter X=-1, and monotonously increases as X increases to reach .pi./2 when parameter X=+1. Function f.sub.1 (X) assumes 1 when parameter X=-1 or +1, and assumes 1/.sqroot.2 when X=0. Accordingly, the l.u.b. (least upper bound) f.sub.1 (X) and the g.l.b. (greatest lower bound) f.sub.1 (X) of f.sub.1 (X) are represented as follows: ##EQU3## Values for E which have one-to-one correspondence to the values for the parameter X can be obtained from equation (10), as by: EQU E.fwdarw.+.infin.(X.fwdarw.+1), EQU E=0 (X=0), EQU E.fwdarw.-.infin.(X.fwdarw.-1).
As is apparent from the foregoing description, values for each of .phi..sub.1 (X) and f.sub.1 (X) have one-to-one correspondence to values for E. The phase component sP of output signal ip, i.e., the amount of phase shift increases from zero to .pi./2 when the control voltage E increases from -.infin. to +.infin.. Also, the amplitude component sA varies together with the variation of the phase component so that it assumes 1 when E approaches -.infin. or +.infin. and assumes 1/.sqroot.2 when E=0. Namely, the amplitude component sA goes down to a value corresponding to 1/.sqroot.2 times the upper limit value at the time when E approaches -.infin. or +.infin.. Moreover, the amount of phase shift assumes .pi./4 at that time.
The conventional phase control circuit has a drawback that the amplitude of an output signal significantly varies to produce a .sqroot.2-fold variation within the entire variable range of the phase of the output signal.